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 SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E - DECEMBER 1982 - REVISED AUGUST 2003
D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-A Max ICC Typical tpd = 10 ns
SN54HC86 . . . J OR W PACKAGE SN74HC86 . . . D, N, NS, OR PW PACKAGE (TOP VIEW)
D D D
4-mA Output Drive at 5 V Low Input Current of 1 A Max True Logic
SN54HC86 . . . FK PACKAGE (TOP VIEW)
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4B 4A 4Y 3B 3A 3Y
1B 1A NC VCC 4B 1Y NC 2A NC 2B
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
4A NC 4Y NC 3B
NC - No internal connection
description/ordering information
These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function Y=A B or Y = AB + AB in positive logic. A common application is as a true / complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. ORDERING INFORMATION
TA PDIP - N SOIC - D -40C 85C -40 C to 85 C SOP - NS TSSOP - PW CDIP - J -55C 125C -55 C to 125 C CFP - W LCCC - FK PACKAGE Tube of 25 Tube of 50 Reel of 2500 Reel of 250 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC86N SN74HC86D SN74HC86DR SN74HC86DT SN74HC86NSR SN74HC86PW SN74HC86PWR SN74HC86PWT SNJ54HC86J SNJ54HC86W SNJ54HC86FK SNJ54HC86J SNJ54HC86W HC86 HC86 HC86 TOP-SIDE MARKING SN74HC86N
SNJ54HC86FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
1
SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E - DECEMBER 1982 - REVISED AUGUST 2003
FUNCTION TABLE (each gate) INPUTS A L L H H B L H L H OUTPUT Y L H H L
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.
Exclusive OR =1
These are five equivalent exclusive-OR symbols valid for an 'HC86 gate in positive logic; negation may be shown at any two ports.
Logic Identity Element = The output is active (low) if all inputs stand at the same logic level (i.e., A = B). Even-Parity Element 2k The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. Odd-Parity Element 2k + 1 The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E - DECEMBER 1982 - REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC86 MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v t/ v Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 2 V VCC = 4.5 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 0 0 NOM 5 MAX 6 SN74HC86 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 ns V V V V NOM 5 MAX 6 UNIT V
VCC = 6 V 400 400 TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 A A VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 0.1 0.1 0.1 0.1 0.26 0.26 100 2 10 SN54HC86 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1000 40 10 MAX SN74HC86 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1000 20 10 nA A pF V V MAX UNIT
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E - DECEMBER 1982 - REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V tpd A or B Y 4.5 V 6V 2V tt Y 4.5 V 6V MIN TA = 25C TYP MAX 40 12 10 28 8 6 100 20 17 75 15 13 SN54HC86 MIN MAX 150 30 25 110 22 19 SN74HC86 MIN MAX 125 25 21 95 19 16 ns ns UNIT
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS No load TYP 35 UNIT pF
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output Input VCC 50% tPLH 50% 10% tPHL Out-of-Phase Output 90% 50% 10% tf 90% tr Input 50% 10% 90% 90% VCC 50% 10% 0 V tf tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL
LOAD CIRCUIT
tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2005
PACKAGING INFORMATION
Orderable Device 84046012A 8404601CA 8404601DA JM38510/65202BCA SN54HC86J SN74HC86D SN74HC86DE4 SN74HC86DR SN74HC86DRE4 SN74HC86DT SN74HC86DTE4 SN74HC86N SN74HC86NE4 SN74HC86NSR SN74HC86NSRE4 SN74HC86PW SN74HC86PWE4 SN74HC86PWLE SN74HC86PWR SN74HC86PWRE4 SN74HC86PWT SN74HC86PWTE4 SNJ54HC86FK SNJ54HC86J SNJ54HC86W
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type LCCC CDIP CFP CDIP CDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SO SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP LCCC CDIP CFP
Package Drawing FK J W J J D D D D D D N N NS NS PW PW PW PW PW PW PW FK J W
Pins Package Eco Plan (2) Qty 20 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 20 14 14 1 1 1 1 1 50 50 TBD TBD TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish Call TI Call TI Call TI Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI Call TI
MSL Peak Temp (3) Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-NC-NC-NC Level-NC-NC-NC Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 250 250 1 1 1 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD TBD TBD
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2005
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B - OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
1
2
3
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
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MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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